Design and Implementation of a Scalable and Efficient FIR Filter Based on FPGA

摘要：

　　This paper studied the algorithms and the structures of FPGA implementation for Finite Impulse Response (FIR) filter, on this basis, a scheme with controlled filter order, and a folded parallel-pipeline structure was adopted designed to balance the resource consumption and computing speed.Combining with the Park-McClellan method to calculate the filter coefficients, the scheme was implemented on the Xilinx Virtex5 FPGA, and it was proved to be feasible and more efficient.

关键词： FPGA FIR filter Controlled Folded parallel-pipeline Park-McClellan

作者: Duoli Zhang Hao Wang Yukun Songc

作者单位: Institute of VLSI Design, Hefei University of Technology, Hefei 230009, Anhui, China

会议类型: 国际会议

会议名称: International Conference on Computational Science and Engineering Applications(CSEA2015)2015计算机科学与工程应用国际会议

会议地点: 三亚

会议语种:英文

页码: 682-688

在线出版日期: 2015-12-26（万方平台首次上网日期，不代表论文的发表时间）