Memory Bandwidth and Energy Efficiency Optimization of Deep Convolutional Neural Network Accelerators
Deep convolutional neural networks(DNNs)achieve state of-the-art accuracy but at the cost of massive computation and memory operations.Although highly-parallel devices effectively meet the requirements of computation,energy efficiency is still a tough nut.In this paper,we present two novel computation sequences,NHWC fine and NHWC coarse,for the DNN accelerators.Then we combine two computation sequences with appropriate data layouts.The proposed modes enable continuous memory access patterns and reduce the number of memory accesses,which is achieved by leveraging and transforming the local data reuse of weights and feature maps in high dimensional convolutions.Experiments with various convolutional layers show that the proposed modes made up of computing sequences and data layouts are more energy efficient than the baseline mode on various networks.The reduction for total energy consumption is up to 4.10×.The reduction for the off-chip memory access latency is up to 5.11×.
Deep learning Convolutional neural network Acceleration Memory efficiency Data layout
Zikai Nie Zhisheng Li Lei Wang Shasha Guo Qiang Dou
National University of Defense Technology,Changsha,China
国际会议
the 12th Conference on Advanced Computer Architecture?(ACA 2018)(2018年全国计算机体系结构学术年会)
辽宁营口
英文
15-29
2018-08-10（万方平台首次上网日期，不代表论文的发表时间）