The Design of Reconfigurable Instruction Set Processor Based on ARM Architecture

摘要：

　　In embedded system,performance and flexibility are two of the most important concerns.To solve the problem of the flexibility of GPP(General Purpose Processor)and the performance of ASIC(Application Specific Integrated Circuit),an ARM based RISP(Reconfigurable Instruction Set Processor)architecture is proposed in this paper which adopts partial reconfiguration and coprocessor mechanism to realize the dynamic online reconfiguration of the processor instruction.A prototype system of the architecture is implemented on Xilinx KC705 FPGA and reconfigurable resource management software is designed and developed for the prototype system.DES encryption/decryption algorithms are tested with prototype,and the test results show that the architecture has the both flexibility of GPP and the performance of ASIC,so it has a wide application prospect.

关键词： RISP Partial reconfiguration Coprocessor Reconfigurable resource management

作者: Jinyong Yin Zhenpeng Xu Xinmo Fang Xihao Zhou

作者单位: Jiangsu Automation Research Institute,Lianyungang 222061,Peoples Republic of China Nanjing University of Post and Telecommunication,Nanjing 210094,Peoples Republic of China

会议类型: 国际会议

会议名称: the 12th Conference on Advanced Computer Architecture?(ACA 2018)(2018年全国计算机体系结构学术年会)

会议地点: 辽宁营口

会议语种:英文

页码: 66-78

在线出版日期: 2018-08-10（万方平台首次上网日期，不代表论文的发表时间）