A scalable ASIP for BP Polar decoding with multiple code lengths

摘要：

　　In this paper,we propose a flexible scalable BP Polar decoding application-specific instruction set processor(PASIP)that supports multiple code lengths(64 to 4096)and any code rates.High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data(SIMD)based architecture and specially designed Polar decoding acceleration instructions.The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2.PASIP provides the maximum throughput of 1563 Mbps(for N = 1024)at the work frequency of 400MHz.The comparison with state-of-art Polar decoders reveals PASIPs high area efficiency.

作者: Wan Qiao Dake Liu

作者单位: The Institute of Application Specific Instruction-set Processor,Beijing Institute of Technology,5 South Zhongguancun Street,Haidian District,100081,Beijing,China

会议类型: 国际会议

会议名称: 2018 2nd International Conference on Electronic Information Technology and Computer Engineering (EITCE 2018)(2018第二届电子信息技术与计算机工程国际会议)(EITCE2018)

会议地点: 上海

会议语种:英文

页码: 1-7

在线出版日期: 2018-10-12（万方平台首次上网日期，不代表论文的发表时间）