Improved Simulated Annealing Genetic Algorithm based Low power mapping for 3D NoC

摘要：

　　Mapping of IP(Intellectual Property)cores onto NoC(Network-on-Chip)architectures is a key step in NoCbased designs.Energy is the key parameter to measure the designs.Therefore,we propose an Improved Simulated Annealing Genetic Alogrithm,abbreviated as ISAGA.The algorithm combines the parallelism of Genetic Algorithm(GA)and the local search ability of Simulated Annealing(SA).We improve the initial population selection of GA to get the lower power consumption mapping scheme.The experimental results show that compared with the GA,ISAGA has good convergence and can search the optimal solution quickly,which can effectively reduce the power consumption of the system.In the case of 124 IP cores,the average power consumption of the ISAGA is reduced by 32.0%compared with the GA.

作者: Hanna He Fang Fang Wei Wang

作者单位: Hefei University of Technology,230009 HeFei,China;School of Computer Science and Information Enginee Hefei University of Technology,230009 HeFei,China

会议类型: 国际会议

会议名称: 2018 2nd International Conference on Electronic Information Technology and Computer Engineering (EITCE 2018)(2018第二届电子信息技术与计算机工程国际会议)(EITCE2018)

会议地点: 上海

会议语种:英文

页码: 1-7

在线出版日期: 2018-10-12（万方平台首次上网日期，不代表论文的发表时间）