A Bit Sampled Wake-Up Receiver with Logarithmic Detector Architecture

摘要：

　　The bit sampled wake up receiver,providing both low sensitivity and low power consumption,is very competitive against other wake up receivers.In this paper,a bit sampled wake-up receiver with logarithmic detector architecture is presented.Theoretically,the proposed receiver has the lower sensitivity than tuned RF receiver of the same amplification gain,which majorly determines the overall power of the receiver.Also we conducted an experiment with the off the shelf circuit to measure the performance of the proposed receiver.According to our test,this receiver is able to give the scalable current consumption from 3.1??A to 146.5??A at the data rate from 10bps to 1kbps accordingly.The sensitivity of the circuit can reach-77dBm regardless of data rate.

关键词： Wake up receiver bit-sampled logarithmic detector

作者: Tao Ma

作者单位: School of Telecommunication Engineering,Xidian University Xian,China

会议类型: 国际会议

会议名称: 第九届网络分布式计算与知识发现国际会议( 2017 International Conference on Cyber-enabled distributed computing and knowledge discovery)

会议地点: 南京

会议语种:英文

页码: 445-449

在线出版日期: 2017-10-12（万方平台首次上网日期，不代表论文的发表时间）