A Self-Calibrated Multiphase Timing System in Time-interleaved ADC

摘要：

　　A precise timing system that consists of two delaylocked loops(DLLs)is proposed to align the sampling phases of the time-interleaved ADC(TI-ADC)with the front-end Sample and Hold(S/H)clock.DLL1 using bang-bang phase detector(PD)handles the 1 GHz system clock and DLL2 produces 32 phases to generate the non-overlapped clock in the followed 4 pipeline ADCs.A new self-calibration scheme in DLL2 is proposed to reduce the mismatch-induced timing skew among multiphase clocks,thereby improving the performance of the S/H in the gain phase.The timing system is verified in 0.18 um CMOS process.The simulation results show that the precision of the calibration loop is 5 ps covering ±75 ps range.

关键词： pipeline ADC DLL PD S/H self-calibrated DRPD Time-interleaved TCC

作者: Jie Sun Jianhui Wu

作者单位: National ASIC system engineering research center Southeast University Nanjing,210096 P.R.China

会议类型: 国际会议

会议名称: 2017 IEEE 2nd Advanced Information Technology,Electronic and Automation Control Conference(IAEAC 2017)(2017 IEEE 第2届先进信息技术、电子与自动化控制国际会议)

会议地点: 重庆

会议语种:英文

页码: 292-295

在线出版日期: 2017-03-25（万方平台首次上网日期，不代表论文的发表时间）