An Asynchronous Design Method and Its Application on a Low-power RFID Baseband Processor
With the rapid development of VLSI technique and the continuous improvement of application requirement,problems such as power consumption and clock skew of integrated circuit have become more and more serious.Because of having several advantages such as low power,high performance and elimination of global clock,asynchronous circuit and its design methodology have been paid more attention in recent years.An asynchronous design and implementation flow based on Balsa and synchronous tools has been firstly proposed in this paper,and GTECH-based optimization scheme and Black-box-based optimization scheme are embedded to reduce area and power.And then design methodology mixed with asynchronous circuit and synchronous circuit is proposed to meet the low power requirement of RFID baseband processor.Finally,our proposed RFID is carried out with an 180nm CMOS technology.Experimental results show that the power of our proposed RFID is less than one third of those of its synchronous counterparts,and our proposed RFID baseband processor can be easily integrated into an UHF RFID chip.
Asynchronous Balsa optimization scheme partition method interface ASIC
Qihui Zhang Jian Cao Xixin Cao Xing Zhang Shijuan Zhang Xianfeng Li Hai Xiao
School of Software and Microelectronics Peking University Beijing,China RFID Business Unit Huada Semiconductor Co.,Ltd.Beijing,China
国际会议
重庆
英文
328-331
2017-03-25（万方平台首次上网日期，不代表论文的发表时间）