An FPGA fast combination placement optimization algorithm research
With the scale of FPGA increasingly becoming larger than before,how to spend less time to reduce the total length of the interconnections to ensure the quality of the placement algorithm needs to be considered as an important issue.In this paper,a fast placement combinatorial algorithm is proposed.The local optimization of the BLE level is implemented by using the low-temperature simulated annealing algorithm after the global placement is completed by adding the fixed point as the force-guided quadratic analytic algorithm.The experimental results have shown that the algorithm is of high quality and with fast speed,which can be successfully applied to industry application.
placement quadratic analytic algorithm low temperature simulated annealing local optimization
Kang Wang Ning Xu Kai Hu
School of Information Engineering,Wuhan University of Technology,Wuhan,China The 58th Research Institute,CETC,Wuxi,China
国际会议
重庆
英文
1258-1262
2017-03-25（万方平台首次上网日期，不代表论文的发表时间）