An Energy-Efficient SAR ADC With a Partial-Monotonic Capacitor Switching Technique

摘要：

　　This paper introduces a highly energy-efficient 12-bit 280KS/s successive approximation register(SAR)analog-to-digital converter(ADC).A novel switching scheme integrated segmentation capacitor and partial-monotonic capacitor technique which can reduce the power consumption and the area is proposed.Compared with the conventional scheme,the average switching energy can be reduced by about 98%.Compared with the monotonic switching scheme,this scheme also provides another important advantage that the change of the signal common-mode voltage will be reduced by half.The proposed ADC was designed in a 0.18-μm 1P6M CMOS process,and the simulation results show that the ADC achieves an SNDR of 68.18dB and an SFDR of 79.08dB with a 280KS/s sampling rate consuming 50μA current.

关键词： SAR ADC partial-monotonic switching techinique low power switching energy

作者: Xiang Hong Chenchen Yang Xiaojie Zhang

作者单位: School of Information and Electronics Beijing Institute of Technology Beijing,China

会议类型: 国际会议

会议名称: 2017 IEEE 2nd Advanced Information Technology,Electronic and Automation Control Conference(IAEAC 2017)(2017 IEEE 第2届先进信息技术、电子与自动化控制国际会议)

会议地点: 重庆

会议语种:英文

页码: 2050-2054

在线出版日期: 2017-03-25（万方平台首次上网日期，不代表论文的发表时间）