A 10bit 40MS/s SAR ADC in 0.18μm CMOS with Redundancy Compensation

摘要：

　　A 10bit 40MS/s asynchronous timing logic successive approximation analog-to-digital converter(SAR ADC)is presented,including a bootstrapped switch,a charge redistribution digital-to-analog converter(DAC)and a dynamic comparator.A redundancy compensation and a mismatch calibration are introduced to achieve conversion accuracy improvement.A monotonic capacitor switching technique is adopted to reduce the power consumption during conversion.The design of ADC was based on SMIC 0.18μm CMOS process and consumes 5.4mA at 1.8 V power supply.The SAR ADC exhibits an SNR and SFDR of 60.27dB and 65.58dB,respectively.

关键词： SAR ADC asynchronous timing logic redundancy compensation mismatch calibration monotonic capacitor switching

作者: Liyang Guo Maodong Wang Xiaojie Zhang Xinghua Wang

作者单位: Institute of Microelectronics,School of Information technology and electronics Beijing Institute of Technology,Beijing China

会议类型: 国际会议

会议名称: 2017 IEEE 2nd Advanced Information Technology,Electronic and Automation Control Conference(IAEAC 2017)(2017 IEEE 第2届先进信息技术、电子与自动化控制国际会议)

会议地点: 重庆

会议语种:英文

页码: 2536-2540

在线出版日期: 2017-03-25（万方平台首次上网日期，不代表论文的发表时间）