Design and Implementation of Delay Measurement Switch in Intelligent Substation Process Level Using FPGA
Constructing SMV network of intelligent substation process layer with switches has been becoming a fashion. This structure is convenient to share information among multiple devices, but it leads to uncertainty and indeterminacy in terms of time delay when SMV packets transmitting in the network. This drawback requires a reliable clock to realize synchronization, and the merging unit should have the ability of timing keeping to a certain degree. To solve these problems, this paper gives a structure of switch based on FPGA aiming to measure the time delay of SMV packets transmission, and proposes a scheme of measuring and storing the time delay using the reserved bytes in IEC 61850-9-2 frame. FPGA realization and experiments justify the proposed structure and scheme of time delay measurement.
intelligent substation process layer sampled measured value (SMV) IEC 61850-9-2 FPGA
Jingmi Liu Yan Li Gui Yang
NR Electric Co.,Ltd.,Nanjing 211100,China
国际会议
西安
英文
1-5
2016-09-01（万方平台首次上网日期，不代表论文的发表时间）