DPSK signal carrier synchronization module implemented on the FPGA

摘要：

　　This paper proposes a method to implement the modified square loop digitally on the FPGA to solve the problem,that the divide circuit in the traditional square loop is difficult to achieve.The modified square loop has a similar structure to the traditional square loop.The method of modified square loop is to multiply quadrature output together to replace the divide circuit.In this paper,a specific method is given to digitize the square loop.The output carrier signal and the frequency difference will be analyzed in the condition of different initial frequency offset,parameters of the loop filter and input SNR.

关键词： digital phase-locked loop square loop carrier synchronization FPGA

作者: Yufei Yang Zhuoming Li Ricai Tian Xiaolin Zhang

作者单位: School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin, China;Sci School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin, China School of Information and Communication Engineering, Harbin Engineering University, Harbin, China

会议类型: 国际会议

会议名称: 2016 Sixth International Conference on Instrumentation and Measurement,Computer,Communication and Control (IMCCC2016)(第六届仪器测量、计算机通信与控制国际会议)

会议地点: 哈尔滨

会议语种:英文

页码: 1015-1020

在线出版日期: 2016-07-21（万方平台首次上网日期，不代表论文的发表时间）