Dynamically Reconfigurable FIR Filter Design Based on FPGA

摘要：

　　The traditional FIR filters based on reconfiguration have disadvantages with difficult to control and low-level automation. In addition, the traditional FIR filters take long time to configure. To solve these problems, a real-time reconfigurable FIR filter is proposed which is based on the dynamic partial reconfiguration technology of EAPR and based on multiplyaccumulate structure. Finding the common and distinguish part by analyze the transfer function of the FIR filters within 1-15 order. Then the FIR filters are divided into static region and reconfigurable region. The design is proposed for the FPGA implementation of the reconfigurable FIR filter, which supports up to 121.265MHz operating frequency and 360KB file size about reconfiguration time is 4.57ms, when implemented in the Xilinx Virtex-5 FPGA device.

关键词： FIR filter FPGA dynamic partial reconfiguration

作者: Guangquan Zhao Qiangqiang Ge Yigang Zhang

作者单位: Department of Automatic Test and Control,Harbin Institute of Technology Harbin,China

会议类型: 国际会议

会议名称: 2015 Fifth International Conference on Instrumentation and Measurement,Computer,Communication and Control (IMCCC2015)(第五届仪器测量、计算机通信与控制国际会议)

会议地点: 秦皇岛

会议语种:英文

页码: 1631-1635

在线出版日期: 2015-09-18（万方平台首次上网日期，不代表论文的发表时间）