Research of Graphical IEC 61850 Modeling and Automatic Processing
The maintenance of the model for an IEC 61850enabled IED is a complexity and error-proven work.Automatic generation the model is an effective measure, the paper discussed several issues encountered in the practice.The paper presents a graphical modeling scheme for IEC 61850 IEDs, with which the logic nodes and the mapping between IEC61850 data entity and IED internal signals are defined graphically.The process level interface for GOOSE and SV often need to be adapted to different application scenarios in digital substations.The paper proposes a decoupled model for process IO interface, with which the IED R&D engineer can define the internal fundamental virtual terminals for process level IOs, and the project design engineer can defme the actual virtual terminals by extending the terminals or add some simple logics according the requirements of the project.An incremental 1EC 61850 model updating algorithm is also introduced.It keeps the model of the functions that are unchanged when re-configuring the functions of an IED, and eliminates the massive work that may be introduced for the updating.The paper also puts forward a clipping method for the modeling file which could effectively decrease the file size and memory consumption of an IED.
Graphical modeling IEC 61850 Process level configuration
Yadong Feng Guodong Wang Hongjun Chen Jifeng Wen Quanrong Shen Songlin Chen
Department of Electrical Engineering,Tsinghua University
国际会议
南京
英文
204-208
2015-09-21（万方平台首次上网日期，不代表论文的发表时间）