Topology Error Identification Method Based on Active Power Estimation of Switch Branch
Topology errors occur frequently in the actually networks, which seriously affect the calculation precision of Real Time State Estimation (RTSE), even result to divergence of state estimation.The paper presents a topology error identification method based on active power estimation of logical switch after summarizing the existing topology error identification methods.The method gives the new logical switch branch model, which the state of the devices such as lines, transformers and generators connect to the logical nodes, nodes in the computed model is equivalent to a logical switch branches.The devices which is connected by logical switch branches will be equivalent to the logical nodes.The least squares estimation method will be used for solving logical switch active power flow and comparison with measurement values, and only the active power flow measurements are used in the method.Based on the results of the linear state estimation the topology errors can be easily judged just by logical rules which is mainly determined by comparing the measurements from SCADA and the estimated value from the linear state estimation.The method significantly improves the speed as the model simplified and the linear calculation guarantees stability without iterative computing.The effectiveness of the method is confirmed by simulation with IEEE 39 nodes system and a practical power system.The method can be used as auxiliary functions of the RTSE to check and modify the topology error of measurements before the calculation of RTSE, which further improve state estimation calculation accuracy.
Active power flow estimation Logical switch branch State estimation Topology error identification Weighted least square (WSL) method
Yi Wang Yan Li
NARI Technology Development Co.Ld,Nanjing 211000 China
国际会议
南京
英文
598-602
2015-09-21（万方平台首次上网日期，不代表论文的发表时间）