A 0.5-mA Ultra-Low-Power Low Noise Amplifier in 0.13μm CMOS

摘要：

　　This paper presents an ultra-low-power design technique for CMOS low noise amplifiers.Parallel capacitance with input transistor Cgs is discussed for reducing gate induced noise and make it an effective way to implement low power LNA with small transistor size and moderate biasing condition.This technique is more effective for advanced process with high transition frequency.A low power LNA is implemented with 0.13μm CMOS,whose current is 0.5mA at l.2V power supply.The noise figure is as low as 0.54dB while power gain is higher than 17dB.

关键词： low noise amplifier low power CMOS noise figure power gain

作者: Yuanfu Zhao Wei Wu Wu Wen Weimin Li Xunping Hou

作者单位: Beijing Microelectronics Technology Institute No.2, N. Siyingmen Rd., Donggaodi, Fengtai District, Beijing 100076, China

会议类型: 国际会议

会议名称: 2015 IEEE Advanced Information Technology, Electronic and Automation Control Conference(IAEAC 2015)(2015 IEEE先进信息技术,电子与自动化控制国际会议)

会议地点: 重庆

会议语种:英文

页码: 31-34

在线出版日期: 2015-12-19（万方平台首次上网日期，不代表论文的发表时间）