FPGA Implementation of Rate Control for JPEG2000

摘要：

　　This paper presents a FPGA implementation of rate control system for JPEG2000. The input image is discrete wavelet transformed, and the wavelet coefficients are encoded by Tier1 coding with rate distortion estimation. During the process of the Tier1 coding, the bit rate for each code block is allocated and the bit stream is then truncated to produce the final bit stream. The Verilog HDL modules for the rate control systemare designed, simulated and synthesized to Alteras FPGA. The result shows that the architecture proposed in this paper is correct.

关键词： JPEG2000 Rate control Tier1 coding Rate distortion estimation FPGA

作者: Shijie Qiao Aiqing Yi Yuan Yang

作者单位: Department of Electronic Engineering, Xian University of Technology, Xian, China

会议类型: 国际会议

会议名称: 2015 Joint International Mechanical,Electronic and Information Technology Conference(JIMET 2015)(2015 联合国际机械,电子与信息技术国际会议)

会议地点: 重庆

会议语种:英文

页码: 230-234

在线出版日期: 2015-12-18（万方平台首次上网日期，不代表论文的发表时间）