SRS:A Split-Range Shared Memory Consistency Model for Thousand-Core Processors
A novel memory consistency model for thousand-core processors is presented.The model simplifies cache coherence for the full chip,and reduces cache design complexity.In addition,the model has the ability to describe the direct exchange of data on chip,thereby alleviating the off-chip memory bandwidth requirements.The paper gives a formal definition of the model,and proves that the model is sequentially consistent.All aspects of the definition are fully used in the process of proof,which means that there is no redundancy in the definition.Therefore,based on the split-range shared memory consistency model,a shared memory system can achieve high performance at low hardware cost.Meanwhile,the model is easy to be understood and used by programmers.
many-core processor memory system memory consistency model sequential consistency formal description
Hui Lyu Fang Zheng Xianghui Xie
State Key Laboratory of Mathematical Engineering and Advanced Computing,Wuxi
国际会议
ACA,Advanced Computer Architecture(2014年全国计算机体系结构学术会议)
沈阳
英文
31-42
2014-08-23(万方平台首次上网日期,不代表论文的发表时间)