Study of Metal Mask Assisted TSV Bottom the Dielectric Layer Etching Process

摘要：

　　TSV CIS package technology is based on a via-last approach in association with an adapted bonding for optical applications.With the gradual increase of the CIS pixel and package integration density,CIS packaging requirements are also increasing.High aspect ratio TSV advantage is gradually reflected.The 3D stacking technology with TSV will be the future development trend of CIS package.In order to complete the bottom of the TSV etch process,we need to protect the wafer surface dielectric layer.In this paper,we use aluminum as a mask to protect the wafer surface silicon oxide dielectric layer.Aluminum with the thickness of 150nm doesnt meet the requirement of the silicon oxide of TSV bottom etching.However,Aluminum with the thickness of 200nm and 300nm can play a role of the etching mask.And Aluminum mask with the thickness of 300nm can withstand 400s of etching time.

关键词： TSV bottom etching metal mask via-last dielectric layer

作者: Fengwei Dai Zhongcai Niu Wenqi Zhang

作者单位: National Center for Advanced Packaging

会议类型: 国际会议

会议名称: The 15th International Conference on Electronic Packaging Technology (ICEPT 2014) ) (第十五届电子封装技术国际会议)

会议地点: 成都

会议语种:英文

页码: 418-421

在线出版日期: 2014-08-12（万方平台首次上网日期，不代表论文的发表时间）