Spray Coating Process with Polymer Material for Insulation in CIS-TSV Wafer-Level-Packaging
This paper presents a novel spray coating process for the forming of sidewall insulation of through silicon via(TSV)which was a challenging process in CMOS image sensor(CIS)packaging.In conventional way,silicon oxide by plasma enhanced chemical vapor deposition(PECVD)is chosen as insulation material.In this paper,one kind of phenolic aldehyde polymer is deposited on the sidewall of though silicon via with the diameter of 75μm and depth of 100μm by novel spray coating process.To avoid the failure of TSV sidewall insulation and electrical interconnection characteristic,the thickness of polymer on the sidewall should be not less than 2μm.To achieve the insulation layer thickness target value,the temperature of spray coating process temperature was adjusted to control the viscosity of polymer.After the process optimization,the minimum thickness of sidewall polymer insulation layer is over 2.5μm meanwhile the conformal coverage characters of sidewall insulation layers are promoted.
CMOS Image Sensor (CIS) Through Silicon Via (TSV) Spray Coating Polymer
Yuechen Zhuang Daquan Yu Fengwei Dai Guoping Zhang Jun Fan
National Center for Advanced Packaging(NCAP China),Wuxi,214135,P.R.China;Institute of Microelectroni Institute of Microelectronics,Chinese Academy of Sciences,Beijing,100029,P.R.China Shenzhen Institute of Advanced Technology,Chinese Academy of Sciences,Shenzhen,518055,P.R.China HuaTian Technology(Kunshan)Co.,Ltd,Kunshan,215300,P.R.China
国际会议
The 15th International Conference on Electronic Packaging Technology (ICEPT 2014) ) (第十五届电子封装技术国际会议)
成都
英文
437-440
2014-08-12（万方平台首次上网日期，不代表论文的发表时间）