Design of 4GHz Multiplier Based on Sigma-Delta Modulation in a 0.18-μm CMOS Technology
This paper presents an implementation of a high speed multiplier for direct sigma-delta modulated digital signals.Compared with some other conventional structures,this multiplier can reduce the circuit-loop delay and work efficiently at a high speed.The mulitpliers circuit has also been improved with a pipe-line structure and the source coupled logic(SCL)technology.It is fabricated in a TSMCs 0.18-μm CMOS process.Simulation results show that the chip meets the function and performance demand of the design and have zero bit error ratio(BER)at a frequency higher than 4GHz.Analysis of the multipliers noise performance is also presented.
Xiao-Dan Guo Qiao Meng Yiong Liang
Institute of RF-& OE-ICs,Southeast University,China;Engineering Research Center of RF-ICs & RF-Systems,Ministry of Education,China
国际会议
Progress in Electromagnetics Research Symposium 2013(2013年电磁学研究新进展学术研讨会)
台北
英文
671-675
2013-03-01（万方平台首次上网日期，不代表论文的发表时间）