Behavioral Modeling of a 12-bit 500-MS/s Multi-stage ADC

摘要：

　　In this paper,a behavioral model of 12-bit@500MS/s pipeline A/D converters(ADCs)and its non-ideal parameters is presented.The proposed model requires 3 stages,the resolution of former two stages is 4.5 bit and the last stage is 4 bit flash architecture.By simulation,the optimum performance is SNDR =73.dB,SFDR =102.3dB,ENOB =11.88 bit when the input signal is 117.7MHz and the sampling clock rate is 500MHz.The proposed model can provide a reference for the error and dynamic analysis for pipeline ADC system.

作者: Wen Wei He Qiao Meng

作者单位: Institution of RF-& OE-ICs,Southeast University,Sipailou 2,Nanjing 210096,China

会议类型: 国际会议

会议名称: Progress in Electromagnetics Research Symposium 2013(2013年电磁学研究新进展学术研讨会)

会议地点: 台北

会议语种:英文

页码: 872-876

在线出版日期: 2013-03-01（万方平台首次上网日期，不代表论文的发表时间）