Design of High Performance Sample Hold Amplifier for Pipeline ADC
A fully-differential switched-capacitor sample-and-hold amplifier (SHA) used in a 10-bit 30-MS/s pipeline analog-to-digital converter (ADC) was designed using a 0.13-μm CMOS process.Flip-around architecture was used in the SHA circuit to lower the power consumption.A gain-boosted operational amplifier (OPAMP) was designed with a DC gain of 87 dB and a unit gain bandwidth of 388MHz at a phase margin of 75 degree.The simulated results have shown that the SHA circuit reaches a spurious free dynamic range (SFDR) of 94 dB and a signal-to-noise ratio (SNR) of 76 dB for a 10.18 MHz input signal with 30 MS/s sampling rate.
Gain-boosted OPAMP switched-capacitor circuit sample hold amplifier pipeline ADC
Rui Zou
College of Electronic and Electrical Engineering, Shanghai University of Engineering Science Shanghai, China
国际会议
重庆
英文
244-247
2015-03-21（万方平台首次上网日期，不代表论文的发表时间）