A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm
Side Channel Analysis (SCA), which has gained wide atten tions during the past decade, has arisen as one of the most critical metrics for the cryptographic algorithm security evaluation.Typical SCA ana lyzes the data-dependent variations inspected from side channel leakages, such as power and electromagnetism (EM), to disclose intra secrets from cryptographic implementations on varying platforms, like microproces sor, FPGA, etc.Dual-rail Precharge Logic (DPL) has proven to be an effective logic-level countermeasure against classic correlation analysis by means of dual-rail compensation protocol.However, the DPL design is hard to be automated on FPGA, and the only published approach is subject to a simplified and partial AES core.In this paper, we present a novel implementation approach applied to a complete AES-128 crypto algorithm.This proposal bases on a partition mechanism which splits the whole algorithm to submodules and transform individuals to DPL format respectively.The main flavor lies within its highly symmetric dual-rail routing networks inside each block, which significantly reduces the routing bias between each routing pair in DPL.This paper describes the overall repair strategy and technical details.The experimental result shows a greatly elevated success rate during the routing repair phase, from lower than 60% to over 84% for Xilinx Virtex-5 FPGA in SASEBO GII evaluation board.
Side Channel Analysis Dual-rail Precharge Logic (DPL) routing repair Design Automation Xilinx FPGA
Chenyang Tu Wei He Neng Gao Eduardo de la Torre Zeyi Liu Limin Liu
State Key Laboratory of Information Security,Institute of Information Engineering,CAS,Beijing,China Centro de Electronica Industrial,Universidad Politecnica de Madrid,Jose Gutierrez Abascal.2,28006 Ma State Key Laboratory of Information Security,Institute of Information Engineering,CAS,Beijing,China
国际会议
福州
英文
217-231
2014-05-05（万方平台首次上网日期，不代表论文的发表时间）