FPGA Implementation and Verification of LDPC Minimum Sum Algorithm Decoder with Weight (3,6) Regular Parity Check Matrix
This work uses a regular parity check matrix with weight (3, 6) on the 5641R plate card of the Software-Defined Radio (SDR) system developed by National Instruments.The Min-Sum Algorithm (MSA) decoder of the Low Density Parity Check (LDPC) codes is completed using the LabVIEW FPGA.Subsequently, integration with the approximate lower triangular LDPC codes complement the complete LDPC encoding and decoding system.In addition to an explicit description of the decoding mechanism of the LDPC-code MSA decoder, analyses of decoding program optimization efficiency and Bit Error Rate (BER) performance curves are conducted.The program simulation results of FPGA indicate that under the additive white Gaussian noise environment, if the BER is 1 E-05, the Signal-to-Noise Ratio (SNR) without using LDPC code is 9.6 dB.The SNR of the LDPC MSA decoder with a min-sum one iteration and ten iterations are 6.8 dB and 6 dB, respectively; the coding gain of the MSA decoder with min-sum one iteration and 10 iterations is 2.8 dB and 3.6 dB, respectively, showing a discrepancy of 0.8 dB.
LDPC approximate lower triangular SDR MSA
Yi-Hua Chen Chang-Lueng Chu Jheng-Shyuan He
Oriental Institute of Technology Institute of Information and Communication Engineering New Taipei city,Taiwan,China
国际会议
哈尔滨
英文
700-704
2013-08-16（万方平台首次上网日期，不代表论文的发表时间）