LOW POWER HARDWARE DESIGN FOR MONTGOMERY MODULAR MULTIPLICATION

摘要：

　　This paper describes the design and implementation of low power modular multiplier of RSA and balances its area and speed.By improving Montgomery modular multiplication algorithm,optimizing critical path and using several low power methods,this paper achieves low power as well as high speed performance.The design is implemented using SMIC 0.13um CMOS process,the average power consumption is 106uW at 13.56MHZ when executing 1024-bit operations,the area is about 0.17mm2 and the time to finish modular multiplication are 1412 clock cycles,such excellent property make it suitable for RSA operation.

关键词： Modular multiplication RSA Montgomery

作者: D.M.Wang Y.Y.Ding J.G.Hu H.Z.Tan

作者单位: 410 Lab.,School of Information Science and Technology,Sun Yat-sen University,Guangzhou,China

会议类型: 国际会议

会议名称: 2013IET International Conference on Information and Communication Technologies(IETICT2013)2013IET信息与通信技术国际会议

会议地点: 北京

会议语种:英文

页码: 99-103

在线出版日期: 2013-04-27（万方平台首次上网日期，不代表论文的发表时间）