Design of Low Voltage Low Power ADC for WSN Node

摘要：

　　This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver.The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology.Post simulation results show that at 1.0-V supply and 16 MS/s,the ADC achieves a SNDR (signal-to-noise-anddistortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB,57.4dB respectively.The total power dissipation is 228tW,and it occupies a chip area of 0.525 mm2.It results in a figure-of merit (FOM) of 0.11 p J/step.

关键词： Analog to Digital Converter SAR Low-power Low-voltage ZigBee

作者: Sikui Ren Zhiqun Li

作者单位: Institute of RF-&OE-ICs,Southeast University,Nanjing,Key Laboratory of Jiangsu Province Sensor Network School of Integrated Circuit,Southeast University,Nanjing

会议类型: 国际会议

会议名称: 2013 2nd international Conference on Opto-Electronics Engineering and Materials Eesearch(2013第二届光电工程与材料研究国际会议)(OEMR2013)

会议地点: 郑州

会议语种:英文

页码: 203-208

在线出版日期: 2013-10-19（万方平台首次上网日期，不代表论文的发表时间）