The Design of High speed and parallel convolutional encoder Based on FPGA
For the channel source of large capacity image data,the error correcting capability and coding efficiency of channel encoding is very important,in order to solve the real-time and parallel of encoding,a kind of code encoding method realized easily by FPGA is proposed.First,the coding principle of the convolutional code is introduced in detail; Secondly,the representation method of the convolutional encoder is elaborated,including the state transition diagram and the grid diagram of the convolutional code; Then,the convolutional encoding algorithm based on FPGA will be converting to achieve rapid,parallel processing method; Finally,(2,1,7) convolutional code algorithm is simulated and tested.The experimental results show that:the convolutionai encoding module is capable of handling the input data stream of up to 160Mbps,processing speed,to meet the parallel and real-time of convolutional encoding for the channel source of large capacity image data,to improve the efficiency ofconvolutional encoding.
Convolutional code Grid diagram Coding efficiency FPGA
Liu Yan-yan Gao Yin-han Chen Guang-qiu Wang En-guo
College of Instrumentation and Electrical Engineering,Jilin University,Changchun 130061,China;School State Key Laboratory of Automobile Simulation and Control,Jilin University,Changchun 130022,China
国际会议
郑州
英文
337-341
2013-10-19（万方平台首次上网日期，不代表论文的发表时间）