Design for realizing arbitrary fractional divider based on FPGA which duty cycle is up to 50%

摘要：

　　This paper proposes a novel method for realizing arbitrary fractional divider based on FPGA.Analyzing the limitations of the existing frequency-divided methods,a new model which consists of two-level dividers is put forward.An arbitrary frequency-divided clock output can be obtained by this method approaching 50% of duty cycle.When the division factor is greater than 128,the duty cycle can be very close to 50% of the clock output.This method is proved to be feasible on the FPGA chip of ALTERA.

关键词： fractional divider FPGA duty cycle

作者: ZHANG Song-wei ZHAO Cheng

作者单位: Dept.of Electronics and Communications Engineering, Zhengzhou Institute of Aeronautical Industry Management, Zhengzhou 450015, China

会议类型: 国际会议

会议名称: 2013 2nd International Symposium on Computer,Communication,Control and Automation(ISCCCA-13)(2013年第二届计算机、通信与自动化国际会议)

会议地点: 太原

会议语种:英文

页码: 58-61

在线出版日期: 2013-04-06（万方平台首次上网日期，不代表论文的发表时间）