Design and implementation of a large points FFT acceleration unit in multi-processor system based on FPGA
This paper introduces the design and implementation of a large points FFT acceleration unit of multi-processor system based on FPGA.It introduces radix-2 DIT-FFT algorithm and the features of hardware platform.It analyzes the FFT acceleration unit overall and divides it into several modules.Then hardware implementations of modules are discussed.The whole FFT acceleration unit is a part of one multi-processor image processing system and the whole system is tested by software and hardware co verification.Results are verified between the software simulation and Virtex6 evaluation board of Xilinx Company.The results are compatible in the range of error.The FFT acceleration unit meets the needs of the whole system and the design is successful.
FFT FPGA Radix-2 DIT-FFT Multi-processor software and hardware co verification
Duo-li Zhang Xue-peng Yang Yu-kun Song
Institute of VLSI design Hefei University of Technology Hefei, Anhui, China
国际会议
太原
英文
830-833
2013-04-06（万方平台首次上网日期，不代表论文的发表时间）