An on-Chip Clock Controller for Testing Fault in System on Chip
In this paper,an on-chip dock (OCC) controller with bypass function based on an internal phase-locked loop (PLL) is designed to test the faults in system on chip (SOC),such as the transition-delay faults and the stuck-at faults.A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller,and then,the test pattern is generated by the automatic test pattern generation (ATPG) tools.Next,the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified.The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timingrelated defects.Finally,the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved,and it is successfully applied to an integrated circuit design.
at-speed scan test on-chip clock transition-delay faults phase-locked loop
Wei Lin Wen-Long Shi
College of Physics & Information Engineering of Fuzhou University Fujian Key Laboratory of Microelectronics & Integrated Circuits Fuzhou,Fujian,P.R.China
国际会议
杭州
英文
1-4
2013-03-22（万方平台首次上网日期，不代表论文的发表时间）