Run-time Leakage Reduction in Near-threshold Circuits with Gate-length Biasing Techniques

摘要：

　　In this paper,we investigate the low leakage design method for near-threshold circuits with gate-length biasing techniques.A cost-effective gate length optimization method is presented.The basic logic gates and two full adders with gate-length biasing technique are implemented and simulated using HSPICE at 45nm CMOS process.The simulation results show that the proposed gates achieved considerable leakage reduction.

关键词： low powert leakage reduction gate-length biasing near-threshold computing

作者: Yangbo Wu Xiaohui Fan Haiyan Ni

作者单位: Faculty of Information Science and Technology,Ningbo University Ningbo,China

会议类型: 国际会议

会议名称: 2013 2nd International Conference on Computer Science and Electronics Engineering(ICCSEE2013)(2013年第二届计算机科学与电子工程国际会议)

会议地点: 杭州

会议语种:英文

页码: 662-665

在线出版日期: 2013-03-22（万方平台首次上网日期，不代表论文的发表时间）