Clock Network Power Saving Using Multi-Bit Flip-Flops in Multiple Voltage Island Design

摘要：

　　Power consumption is an important issue in modern high-frequency and low power design.Multi-bit flip-flops are used to reduce the clock system power.The scaling with multiple supply voltage is an effective way to minimize the dynamic power consumption.In this paper,we propose an effective multi-bit flip-flops merging approach to deal with the clock network power minimization problem and an placement method to avoid placing flip-flops in the congestion bins.Moreover,the proposed approach can be applied to both single and multiple supply voltage designs.Experimental results show that our approach can reduced the clock power up to 25%.In addition,for multiple supply voltage designs,the proposed approach can reduce the number of level shifters significantly.

关键词： Clock network Multi-bit flip-flop Multiple supply voltage Level shifter Low power

作者: Jhen-Hong He Li-Wei Huang Jui-Hung Hung Yu-Cheng Lin Guo-syuan Liou Tsai-Ming Hsieh

作者单位: Department of Information and Computer Engineering,Chung Yuan Christian University Chung-Li,Taiwan,R Faraday Technology Inc.,Taiwan,R.O.C Department of Electronic Engineering,Chung Yuan Christian University,Chung-Li,Taiwan,R.O.C Department of Multimedia and E-Commerce,Kainan University Luzhu Township,Taiwan,R.O.C

会议类型: 国际会议

会议名称: 2013 2nd International Conference on Computer Science and Electronics Engineering(ICCSEE2013)(2013年第二届计算机科学与电子工程国际会议)

会议地点: 杭州

会议语种:英文

页码: 1498-1503

在线出版日期: 2013-03-22（万方平台首次上网日期，不代表论文的发表时间）