Optimum Digital Filter for High-Performance All-Digital Phase-Locked Loop

摘要：

　　The effect of all-digital phase-locked loop (ADPLL) digital filter parameters on the jitter is investigated in time domain,and a systematic design procedure for ADPLL is presented.The pro posed method not only estimates the output jitter of an ADPLL,but also finds the optimal filter pa rameter minimizing the overall ADPLL timing jitter.To verify the theoretic analysis,an ADPLL behavior model in matlab is designed.The simulation shows significant performance improvement on the timing jitter.

关键词： All-digital phase-locked loop (PLL) digital controlled oscillator (DCO) jitter loop gain

作者: Huafang Sun Xinning Liu Xin Chen

作者单位: National ASIC System Engineering Research Center,Southeast University,Nanjing 210096,Peoples Republ College of Electronics and Information Engineering,Nanjing University of Aeronautics & Astro nautics

会议类型: 国际会议

会议名称: 2012 International Applied Mechanics,Mechatronics Automation Symposium(2012应用力学,机电一体化自动化国际研讨会)(IAMMAS2012)

会议地点: 沈阳

会议语种:英文

页码: 587-592

在线出版日期: 2012-09-07（万方平台首次上网日期，不代表论文的发表时间）