Design Methodology for Multipliers with Active Leakage and Dynamic Power Reduction
A novel design methodology for multipliers to reducing both active leakage and dynamic power using dynamic power gating is presented,where sleep transistors are inserted between the real and virtual ground rails of various parts of the multiplier which could be selectively turned on/off.On-chip sleep signals are generated from one input signal of the multiplier which has larger dynamic range.By detecting the magnitude of the input signal,the idle parts of the multiplier are identified and the power gating schemes are dynamically applied even when the multiplier is performing useful computation.Simulations show that the total power dissipation of the proposed multiplier could be reduced up to 39.3% in a typical DSP application.
Multiplier Active leakage Dynamic power Power gating
Tian Xi Qiao Fei Dong Zaiwang Liu Yujun Zhao Yuting
Department of Electronic Engineering,Tsinghua University,Beijing,China Academy of Armored Forces Engineering,Beijing,China Northwestern Polytechnical University,Xian,China
国际会议
沈阳
英文
1440-1445
2012-09-07（万方平台首次上网日期，不代表论文的发表时间）