Design of Real-time Image Collecting Module Based on FPGA
(0) A new pixel collecting interface board based on FPGA is designed,it is a part of conveyer belts fault detection device.The previous systems controller chip CPLD is replaced by FPGA,the memory FIFO chips are replaced by SRAM,the chip CY7C68013 is chosen as the USB 2.0 controller and works in Slave FIFO transmission mode.The firmware program and application program are compiled to transmit data.The Chipscope Pro Tools are used in the system to debug online,and the correctness of data transmission can be analyzed and verified.The experimental results demonstrate that the new pixel collecting interface board has the advantage of high-speed data acquisition,and can transmit data in real time and correctly.It also has a good scalability and can be used into other high-speed acquisition systems.
FPGA USB 2.0 Slave FIFO Collecting Board
Jiangwei Wang Muyan Ma Junmin Leng
35＃ North Fourth Ring Middle Road, Chaoyang District, Beijing, China
国际会议
西安
英文
1095-1099
2012-08-24（万方平台首次上网日期，不代表论文的发表时间）