Implement of a 3D Stacked Module Using Edge-interconnect

摘要：

　　The ever-increasing circuit density and performance of integrated circuit bring the improvement of design difficulty.Edge-interconnect of SIP technology can reduce the design complexity and system size,improve system reliability and performance.This paper presents a CPU packaging configured with three-dimensionally (3D) integrated SRAM,Flash and some peripheral chips.Signal communication between them is achieved by using edge-interconnect which is implemented by several complex processes,stacking,potting,cutting,gilding and laser engraving etc.Heat dissipation of the packaging is also considered.And the end product has passed functional test and environmental test.

作者: Xiongbo Zhao Penglong Jiang Liangliang Liu

作者单位: National Key Laboratory of Science and Technology on Aerospace Intelligent Control,Beijing 100854,China;Beijing Aerospace Automatism Control Institute,Beijing 100854,China(ext.mail box)402 of mail box 142,Beijing,china

会议类型: 国际会议

会议名称: 2012 International Conference on Electronic Packaging Technology & Hiigh Pachaging(2012电子封装和高密度封装国际会议(ICEPT-HDP2012))

会议地点: 桂林

会议语种:英文

页码: 82-84

在线出版日期: 2012-08-13（万方平台首次上网日期，不代表论文的发表时间）