Effects of Via Pitch on Silicon Stress in TSV Interposer

摘要：

　　Through silicon vias (TSVs) have been extensively studied because it is a key enabling technology for achieving three dimensional (3D) chip stacking and silicon interposer interconnection.The large mismatch between the coefficients of thermal expansion (CTE) of copper and silicon induces stress which is critical for the TSV reliability performance.This paper proposes analytical solutions of stress in a single TSV subjected to thermal loading.Then the thermal stress interaction between the vias induced on silicon has been investigated using finite element modeling.It indicates that the interaction of thermal stress between vias becomes insignificant as long as the ratio of pitch to diameter of TSVs reaches three.

作者: AN Tong QIN Fei WU Wei YU Daquan WAN Lixi WANG Jun

作者单位: College of Mechanical Engineering and Applied Electronics Technology,Beijing University of Technolog Institute of Microelectronics of Chinese Academy of Sciences,Beijing 100029,P R China Materials Science Department of Fudan University,Shanghai 200433,P R China

会议类型: 国际会议

会议名称: 2012 International Conference on Electronic Packaging Technology & Hiigh Pachaging(2012电子封装和高密度封装国际会议(ICEPT-HDP2012))

会议地点: 桂林

会议语种:英文

页码: 600-605

在线出版日期: 2012-08-13（万方平台首次上网日期，不代表论文的发表时间）