Integrated Wafer Thinning Process with TSV Electroplating for 3D Stacking

摘要：

　　This paper presents an optimized integrated thinning process which is dedicated to fabricating ultra thin wafers with through silicon via (TSV).The thinning process is based on blind-vias electroplating,mechanical grinding,wet/dry etching,CMP(chemistry mechanical polishing)and a wafer to wafer handling system developed by previous studies1,2.In the study,60um TSV filled with copper is clearly observed in 40-um-thick 4-inch wafers,and the wafer flatness is successfully controlled to be below 5um.Meanwhile,the integrated thinning process is a low-cost one that only demands direct current (DC) electroplating and a relatively short period of CMP process,which may be applicable to industrial production.

作者: Cao Li Shengjun Zhou Run Chen Tao Peng Xuefang Wang Sheng Liu

作者单位: Institute for Microsystems,State Key Lab of Digital Manufacturing Equipment & Technology,School of M State Key Laboratory of Mechanical System and Vibration,School of Mechanical Engineering,Shanghai Ji Institute for Microsystems,State Key Lab of Digital Manufacturing Equipment & Technology,School of M

会议类型: 国际会议

会议名称: 2012 International Conference on Electronic Packaging Technology & Hiigh Pachaging(2012电子封装和高密度封装国际会议(ICEPT-HDP2012))

会议地点: 桂林

会议语种:英文

页码: 945-948

在线出版日期: 2012-08-13（万方平台首次上网日期，不代表论文的发表时间）