Design of IRIG-B Code Encoder Based on SOPC

摘要：

　　Aiming at the complexity of time unified hardware architecture,this paper presents the design scheme of IRIG-B encoder and system control based on SOPC.The NIOSII processor is configured with NIOSII IDE.Firstly,the design of IRIG-B(DC) coding module is accomplished to realize with Verilog HDL,and then IRIG-B(AC) coding module is completed successfully through the DA conversion on the basis of IRIG-B(DC) code.The experiment result shows that the encoder can stably and reliably produce a standard IRIG-B code,and satisfy the application requirements.

关键词： IRIG-B code SOPC NIOSII Time coding

作者: Xu Qiaoyu Wang Xing

作者单位: School of Electromechanical Engineering Henan University of Science and Technology,Luoyang, China School of Electromechanical Engineering Henan University of Science and Technology Luoyang, China

会议类型: 国际会议

会议名称: 2012 2nd International Conference on Computer Application and System Modeling(2012第二届计算机应用与系统建模国际会议)(ICCASM-2012)

会议地点: 沈阳

会议语种:英文

页码: 103-106

在线出版日期: 2012-07-27（万方平台首次上网日期，不代表论文的发表时间）