The Design and Implementation of Parallel Distributed Algorithm FIR filter based on FPGA

摘要：

　　The article proposed a new method for implementing linear phase FIR filter based on FPGA.For the key to implementing the FIR filter on FPGA—multiply-add operation,a parallel distributed algorithm was presented,which is based on LUT.The designed file was described with VHDL and realized on Alteras field programmable gate array (FPGA),giving the design method.The experimental results indicated that the system can run stably at 120MHz or more,which can meet the requirements of signal processing for real-time.

关键词： FIR digital filter DA (distributed algorithm) FPGA LUT Rreal-Time

作者: Baofeng Zhang Dehu Man Junchao Zhu

作者单位: Tianjin Key Laboratory for Control Theory and Application in Complicated Systems,Tianjin University School of Electrical Engineering,Tianjin University of Technology,Tianjin,300384,China

会议类型: 国际会议

会议名称: 2012 International Meeting on Opto-Electronics Engineering and Materials Research(OEMR2012)(2012光电工程与材料国际会议)

会议地点: 沈阳

会议语种:英文

页码: 534-537

在线出版日期: 2012-07-27（万方平台首次上网日期，不代表论文的发表时间）