Improving Device Performance and Variability for 28nm and Beyond Low Power SoC Technology using Advanced Implant Solutions

摘要：

　　Advanced junction scaling with device performance gain,leakage reduction and reduced threshold voltage (Vth) variation are critical for CMOS 28nm node and future scaling.In this paper,implant induced defect engineering for higher drive current with reduced SRAM defectivity,advanced junction formation and Vth mismatch (Vtmin) on a state-of-the-art 28nm logic flow are demonstrated and discussed.

关键词： Novel process technology ion implantation cryo implant strain relaxation process modeling

作者: C.L.Yang Y.L.Chin M.Chan J.Y.Wu I.C.Chen B.Colombeau B.N.Guo T.Wu H.J.Gossmann S.Lu C.I.Li G.P.Lin C.H.Tsai Y.S.Huang C.Fu T.Y.Lu H.Y.Wang W.J.Chen

作者单位: United Microelectronics Corp., Central Research and Development Div., ＃18, Nan-Ke Rd.Ⅱ, Tainan 744, Applied Materials, Silicon Systems Group, Varian Semiconductor Equipment, 35 Dory Road, Gloucester,

会议类型: 国际会议

会议名称: 2012 12th International Workshop on Junction Technology (2012结技术国际研讨会(IWJT-2012))

会议地点: 上海

会议语种:英文

页码: 18-23

在线出版日期: 2012-05-10（万方平台首次上网日期，不代表论文的发表时间）