Reduction of Thermal Induced Pattern Loading and Device Sensitivity by Various Rapid Thermal Processing Models

摘要：

　　Beyond 65nm node,pattern loading effect (PLE) in conventional RTP (front-side heating) has been emerged as a major yield killer.Different pattern and deposited film property strongly influence thermal absorption and emission at the integration stage of the spike anneal (e.g.,STI,poly,and nitride spacers) leadto significant temperature differences across each die.Several methods for reducing the temperature variation have been reported,such as layout modifications and the application of absorption layers.By using these methods,significant improvements can be obtained,but the limitation is layout flexibility and increasing extra cost.

作者: C.Y.Yang C.L.Yang J.Y.Wu C.I.Li C.H.Wei T.M.Yang G.P.Lin W.J.Chen Y.L.Chin R.Liu M.Chan

作者单位: United Microelectronics Corp., Central Research and Development Div., ＃18, Nan-Ke Rd.Ⅱ,Tainan 744, Taiwan

会议类型: 国际会议

会议名称: 2012 12th International Workshop on Junction Technology (2012结技术国际研讨会(IWJT-2012))

会议地点: 上海

会议语种:英文

页码: 73-76

在线出版日期: 2012-05-10（万方平台首次上网日期，不代表论文的发表时间）