Junction vs.Junctionless Vertical MOSFET by Using Partial SOI Structure:A 2D Simulation Study
In this paper,we focus on the electrical characteristics of the partially insulating oxide (PiOX) junctionless vertical MOSFET (JLVFET) and PiOX junction vertical MOSFET (JVFET) through computer simulations.It is clear that the PiOX JLVFEr process is simple due to the absence of the source/drain (S/D) implantation and annealing,thereby reducing the fabrication cost,in whereas the PiOX JVFET needs an S/D implant.But,according to simulation results,we find out that the PiOX JVFETexhibits desired characteristics which are similar to those of the PiOX JLVFET.This means that the subthreshold swing and drain-induced bamer lowering,can be almost the same for both devices.Additionally,the high S/D doping presented in the PiOX JVFET helps reduce the parasitic S/D resistance,resulting in an enhanced current drive.In other words,it is believed that the PiOX JVFET is still considered as a candidate for future CMOS scaling.
Shu-Huan Syu Jyi-Tsong Lin Yi-Chuen Eng Shih-Wen Hsu Kuan-Yu Chen You-Ren Lu
Dept.of Electrical Engineering, National Sun Yat-Sen University 70 Lian-Hai Rd., Kaohsiung 80424, Taiwan, R.O.C
国际会议
2012 12th International Workshop on Junction Technology (2012结技术国际研讨会(IWJT-2012))
上海
英文
172-175
2012-05-10（万方平台首次上网日期，不代表论文的发表时间）