Simulation Study of Junctionless Vertical MOSFETs for Analog Applications

摘要：

　　In this paper,we use the junctionless (JL) technology to design both JL middle-gate vertical MOS (JLMGVMOS) and JL pseudo tri-gate VMOS (JLPTGVMOS) for performance comparison on analog metrics.According to TCAD simulations,the JLPTGVMOS devices demonstrate excellent characteristics,such as high transconductance (gm),transconductance generation factor (gm/Id),and voltage gain Avi,when compared with the JLMGVMOS devices.This is owing to its better gate controllability over the channel charges.Although a larger drain conductance gd,resulting in a smaller drain output resistance ro,is observed for JLPTGVMOS devices compared with JLMGVMOS devices,these results are still within acceptable limits.Additionally,we also find out that the impacts of gate material (n+ poly-Si or p+ poly-Si) on the analog properties merely result in a large threshold voltage shift.

作者: Shih-Wen Hsu Jyi-Tsong Lin Yi-Chuen Eng Shu-Huan Syu Kuan-Yu Chen You-Ren Lu

作者单位: Dept.of Electrical Engineering, National Sun Yat-Sen University 70 Lien-Hai Rd., Kaohsiung 80424, Taiwan, R.O.C

会议类型: 国际会议

会议名称: 2012 12th International Workshop on Junction Technology (2012结技术国际研讨会(IWJT-2012))

会议地点: 上海

会议语种:英文

页码: 226-229

在线出版日期: 2012-05-10（万方平台首次上网日期，不代表论文的发表时间）