Development of Verification Envioronment for SPI Master Interface Using System Verilog

摘要：

　　System-level verification with scalable and reusable components provides a solution for current complex SOC verification and SystemVeriiog with OOP is one of the most promising language to develop a complete verification environment with constrained random testing,functional coverage and assertions.In this paper,a uniform verification environment for SPI master interface is developed using SystemVerilog after a comprehensive analysis of the verification plan.The proposed multi-layer testbench is comprised of APB driver,SPI slave,scoreboard,checker,coverage analysis and assertions,which are implemented with different properties of SystemVerilog.Furthermore,constrained random testing vectors are generated automatically and driven into the DUT for higher functional coverage.The verification result shows the effectiveness of the proposed verification environment,which is of great feasibility for further extension and reuse.

关键词： System Verilog object-oriented programming SPI interface functional coverage assertion

作者: Zhili Zhou Zheng Xie Xinan Wang Teng Wang

作者单位: Key Lab of Integrated Micro-Systems, Peking University Shenzhen Graduate School, Shenzhen, China

会议类型: 国际会议

会议名称: 2012 IEEE 11th International Conference on Signal Processing (第11届IEEE信号处理国际会议)

会议地点: 北京

会议语种:英文

页码: 2188-2192

在线出版日期: 2012-10-21（万方平台首次上网日期，不代表论文的发表时间）