A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme

摘要：

　　Combined with partial dynamic threshold MOSFET connection scheme,a high density 7T subthreshold SRAM bitcell operating at supply voltage of 200 mV is proposed in this paper.Dual write and single read ensures high read static noise margin of the SRAM bitcell without expense of writability degradation.The 7T SRAM exhibits robust efficiency,making the design less vulnerable to process variation.Compared to the referenced 6T and the 8T SRAM bitcell,the proposed bitcell has four aspects of improvement:(1) 5.1% and 6.1% larger hold margin,(2) 80.6% and 85.5% of standard deviation,(3) 50% and 18% reduction of area (at 200 mV),and (4) 16X and 32X bitcells per bitline.To our best knowledge,the area penalty of proposed SRAM is the smallest with robustness and functionality of subthreshold SRAM achieved.

关键词： subthreshold SRAM static noise margin (SNM) high density

作者: Jun Yang Mingqiang Qiu Kai Huang Na Bai

作者单位: National ASIC System Engineering Research Center, Southeast University, Nanjing, China School of Electronics and Information Engineering, Anhui University, Hefei, China National ASIC System Engineering Research Center, Southeast University, Nanjing, China;School of Ele

会议类型: 国际会议

会议名称: the Second International Conference on Frontiers of Manufacturing and Design Science(第二届制造与设计科学国际会议(ICFMD 2011))

会议地点: 台湾

会议语种:英文

页码: 1279-1285

在线出版日期: 2011-12-11（万方平台首次上网日期，不代表论文的发表时间）