FPGA-Based Research on The Hardware Design of CAVLC Encoder

摘要：

　　H.264/AVC video coding standard adopt CAVLC (Context-based Adaptive Variable Length Coding) in Baseline profile and Extended profile,this paper briefly introduces the principle of CAVLC encoding; In the hardware design,the Ping- Pong operation and structure of parallel processing are adopted in order to reduce CAVLC encoded clock cycle and improve the throughput.All hardware circuits are described by Verilog HDL,and are simulated by using Modelsim SE 6.5,and are verified by using ALTERA Cyclone Ⅱ EP2C35F672C8 FPGA.

关键词： H.264/AVC CAVLC FPGA

作者: Jin Xu Jianhua Mao

作者单位: Electronic Information college, Xian Polytechnic University, Xian, Shanxi, P.R.China

会议类型: 国际会议

会议名称: 2013 International Conference on Information, Business and Education Technology (2013信息、商业与教育技术国际会议(ICIBET 2013))

会议地点: 北京

会议语种:英文

页码: 128-131

在线出版日期: 2013-03-14（万方平台首次上网日期，不代表论文的发表时间）