A 4th Order Band Pass Sigma-Delta Modulator Using Carry-Save for Digital IF Quadrature Modulator

摘要：

　　This paper presents a digital intermediate frequency (IF) quadrature modulator realized by a single-bit band pass sigma-delta DAC,in which a pair of single-bit-low-pass sigmadelta digital modulators is used to share the computation for doubling the speed.Fractional-delay interpolation filters are added before the sigma-delta modulators to adjust the interleaved timing relationship between the IQ paths.Carry-save algorithm is used to increase the computation speed in both sigma-delta modulators and interpolation filters,which leads to a speed improvement with little area overhead.The simulation results show that the proposed design can realize a single bit 4th order band pass sigma-delta DAC whose sampling frequency reach hundreds Mhz,and whose SFDR is up to 65 dB.

关键词： 2complement DSP Carry Save Sigma Delta Modulation Modulo Arithmetic

作者: Ruimin Huang Zhen Yan Chaodong Ling Niklas Lotze Yiannos Manoli

作者单位: College of Information Science and Engineering Huaqiao University Xiamen, China Department of Microsystem Engineering, Fritz-Hüttinger-Professur für Mikroelektronik Univ Freiburg F

会议类型: 国际会议

会议名称: 2012 IEEE 14th International Conference on Communication Technology(2012年第十四届通信技术国际会议(ICCT 2012))

会议地点: 成都

会议语种:英文

页码: 1354-1358

在线出版日期: 2012-11-09（万方平台首次上网日期，不代表论文的发表时间）